1. Field of the Invention
This invention relates generally to Integrated Circuits and, in particular, to an interfacing scheme within a programmable logic device (PLD).
2. Description of the Related Art
Traditionally, when a system uses different clock domains in a soft intellectual property (SIP) design, it is assumed that the clocks are asynchronous. Hence, conventional first in-first out (FIFO) phase and/or frequency crosser is normally used between two clock domains. However the area cost to implement the FIFO phase and/or frequency crosser is high since it is typically implemented using regular flip-flops. In addition, the FIFO size (in terms of width) increases proportionally for high bandwidth applications. The FIFO data width is a function of the serializer/de-serializer (SERDES)/dynamic phase alignment (DPA) de-serialization rate. It should be appreciated that a SERDES/DPA operating in 8× mode requires double the FIFO size for one that is operating in 4× mode.
From a full-chip floor plan perspective, the hard intellectual property (HIP) block is typically buried inside the field programmable gate array (FPGA) core fabric. Hence, the connectivity between HIP and SERDES/DPA is achieved using the FPGA soft routing resources, i.e., the horizontal and vertical lines, while the clock signals are routed through the core clock network from a Low Voltage Differential Signaling Phase Lock Loop (LVDSPLL).
FIG. 1 is a simplified schematic diagram illustrating the use of a FIFO phase and/or frequency crosser for a system using two different clock domains. Here, chip 100 includes circuitry operating at a frequency associated with clock domain A 102 and circuitry operating at a frequency associated with clock domain B 106. Communication between the two clock domains proceeds through FIFO 104. Depending upon the bandwidth and the difference between the frequencies of clock A and clock B, a number of flip-flops 104-1 through 104-n are required. As the number of flip-flops increases, so does valuable chip area required to locate these flip-flops.
Another shortcoming of the configuration of FIG. 1 is that the data is supplied to the circuitry associated with the clock domain running at the higher clock frequency according to the slower clock domain frequency. Accordingly, data that is processed in multiple clock cycles, takes much longer to process using the slower clock frequency rather than the higher clock frequency.
As a result, there is a need to solve the problems of the prior art to more efficiently transfer data across different clock domains.